Reconfigurable devices represented by an FPGA (Field Programmable Gate Array) require a very long period of time to read configuration information. As a result, for example, if configuration information is updated many times in order to conduct a test of a reconfigurable device, then the time of reading the configuration information becomes predominant in the test time. Therefore, in order to reduce the time of reading the configuration information, it has been desired to supply compressed data of the configuration information to a reconfigurable device and to expand the compressed data within the reconfigurable device for thereby obtaining the configuration information.
Meanwhile, technology of compressing data for transmission has heretofore been known in the field of data communication (see, e.g., Patent Literature 1).
Furthermore, there has also been known a technique of converting a compression level of data into a level that can be expanded at a receiving side (see, e.g., Patent Literature 2).
Moreover, there has heretofore been known technology of performing a compression depending upon the type of the data (see, e.g., Patent Literature 3).
FIG. 14 is a diagram schematically showing a compression process of data at a transmitting side. A compression tool 141 is operable to compress data (input data) 142 to be transmitted and outputs them as compressed data 143.
FIG. 15 is a diagram schematically showing a related buffer type receiver 150. The buffer type receiver 150 has an expansion circuit 151 and a receiver circuit 152. Furthermore, the buffer type receiver 150 also has a buffer circuit 153 between the expansion circuit 151 and the receiver circuit 152. The compressed data 143 transmitted from the transmitting side are supplied to the expansion circuit 151 and expanded therein. The expanded data are temporarily stored in the buffer circuit 153 and then read by the receiver circuit 152.
FIG. 16 is a graph showing a time-varying expansion speed (output data rate) of the expansion circuit 151. The expansion speed of the expansion circuit 151 is not necessarily constant and varies with passage of time. When the expansion speed of the expansion circuit 151 exceeds a receiving speed (the speed limit or the maximum receiving speed) of the receiver circuit 152, the buffer circuit 153 temporarily stores data that have not been received by the receiver circuit 152 to prevent an overflow of data.
FIG. 17 is a diagram schematically showing a related compressed data conversion device. A conversion circuit 171 temporarily expands high-rate compressed data 173 and converts the expanded data into low-rate compressed data 174 so that an expansion process can be performed in a low-performance expansion circuit 172. With this configuration, an average expansion speed of the low-performance expansion circuit 172 can be improved as shown in FIG. 18.    Patent Literature 1: JP-A 11-154951    Patent Literature 2: JP-A 2000-299664    Patent Literature 3: JP-A 2001-148858